Silicon-on-insulator (SOI) devices offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits.
A drawback in some SOI circuits is the floating body effect. A floating body device/transistor is characterized in that there is (substantially) no effective electrical contact to the body/well of the device/transistor. The floating body effect is the effect of dependence of the body potential of a transistor realized by the silicon on insulator SOI technology on the history of its biasing and the carrier recombination processes. The transistor's body forms a capacitor against the insulated substrate. The charge accumulates on this capacitor and may cause adverse effects, for example, opening of parasitic transistors in the structure and causing off-state leakages, resulting in higher current consumption. It also causes the above-noted history effect, the dependence of the threshold voltage of the transistor on its previous states. Due to the additional isolation of the SOI device, the body or well node is not typically contacted. In principal, body tie structures may be employed in SOI CMOS (complementary metal-oxide semiconductor) to add a contact to the floating body node, but this introduces parasitic resistances and capacitances as well as significant area penalties.
For many digital circuits, this impact can be neglected. However, the stability of certain circuits, such as the commonly used 6T SRAM (6 transistor static random access memory) cell, is degraded due to tolerance issues arising from the floating body. This is typically addressed by increasing the linear threshold voltage (Vt) of the FETs in the array, but this usually results in lowering the overall array performance.
In silicon-on-insulator (SOI) technologies, there are many cases where electrical contact to the normally floating body region is highly desirable. Among these include the mitigation of history effects in SOI and the enablement of low leakage SOI devices and/or high voltage SOI devices. There are many known solutions in the prior art. Almost all of these solutions typically have substantial density and parasitic penalties and many are not self-aligned. Many of them also consume a portion of the device's electrical width. For example, one of the earliest dual-sided Schottky body tie devices was formed by intentionally omitting dopant from a portion of the diffusion region. While effective, the cost of this approach is loss of device electrical width as well as poor gate control from low gate doping in the regions. A later prior art approach uses a Schottky body contact where the diffusion implants are angled in a manner to expose the source silicide to the body. This approach has drawbacks with the masking required and groundrule considerations on the angle that may be employed.
Floating body issues in SOI (silicon on insulator) based SRAM are a critical concern for current and future technologies as they are an inherent source of variability. Severe variability issues threaten SRAM and array functionality unless properly addressed. SRAM design often involves a design tradeoff between stability and performance. While the floating body in SOI devices is beneficial to performance in certain uses, it also has negative impacts on stability and yield through increased variability.
FIG. 1 illustrates a conventional 6T-SRAM layout, with each transistor designated M: those labeled M2 and M4 are pull-up transistors, those labeled M1 and M3 are pull-down transistors, and those labeled M5 and M6 are pass gate or access transistors. Access to the SRAM cell is enabled by the word line (WL) which controls the two pass gate or access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines BL′ and BL. They are used to transfer data for both read and write operations. While it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided since it improves noise margins. During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM speed as compared to DRAM memory, and the symmetric structure of SRAMs also allows for differential signaling which makes small voltage swings more easily detectable. As an additional distinction over DRAM cells, SRAM cells accept all address bits at a time whereas DRAMs have the address multiplexed in two halves (i.e. higher bits followed by lower bits, over the same package pins).
US Pat. Publ. 2007/0242507 describes a technique for assessing floating body effects in SOI circuits and is seen as relevant background to these teachings, as is US Pat. Publ. 2006/175659 which describes using linked bodies in SOI SRAM to mitigate floating body effects. US Pat. Publ. 2006/046408 describes adaptive well biasing SOI devices from wells formed beneath the buried oxide. U.S. Pat. No. 7,274,072 details for a 6T SRAM four distinct cases for the various transistors disposed in the bulk Si region and others in the SOI region. U.S. Pat. No. 7,217,978 describes a SRAM having a peripheral logic portion and a SRAM array portion, of which n-FETs of the peripheral logic portion are fabricated in SOI with floating body regions and p-FETs are fabricated in crystal orientation bulk regions. The SRAM cells detailed herein are seen to differ in structure over those two former US patents, in a manner and with advantages that are detailed further below.